Field of the Invention
The invention relates to a test structure for determining a short circuit between trench capacitors in a memory cell array, the trench capacitors being arranged in matrix form.
Semiconductor memories, in particular dynamic random access semiconductor memories (DRAMs), are composed of a matrix of memory cells which are connected up in the form of rows via word lines and columns via bit lines. Data are read from the memory cells or data are written to the memory cells by the activation of suitable word and bit lines. A dynamic memory cell generally contains a selection transistor and a storage capacitor, the selection transistor usually being configured as a horizontally designed field-effect transistor and comprising two diffusion regions separated by a channel above which a control electrode, a so-called gate, is arranged. The gate is in turn connected to a word line. One of the diffusion regions of the selection transistor is connected to a bit line and the other diffusion region is connected to the storage capacitor. Through the application of a suitable voltage to the gate via the word line, the selection transistor turns on and enables a current flow between the diffusion regions in order to charge the storage capacitor via the connected bit line.
One objective in DRAM memory development is to achieve a highest possible yield of memory cells with good functionality in conjunction additionally with a minimum chip size. Ongoing endeavors to miniaturize the DRAM memory cells have led to the design of memory cells in which, in particular, the storage capacitor utilizes the third dimension. A three-dimensional storage capacitor concept is that of trench capacitors comprising a trench that is etched into the semiconductor substrate and filled with a highly conductive material, which serves as an inner capacitor electrode. By contrast, the outer capacitor electrode is generally formed in buried fashion as a diffusion region in the substrate. The outer capacitor electrode is contact-connected via a further layer formed in buried fashion in the semiconductor substrate, a so-called buried plate. The electrical connection between the diffusion region of the selection transistor and the inner capacitor electrode of the trench capacitor in a memory cell is effected in the upper trench region by an electrode connection usually formed as a diffusion region, the so-called buried strap.
In order to keep the chip size as small as possible and at the same time to provide for a sufficient storage capacitance which ensures a sufficiently large read signal, the trench capacitors are being fabricated with increasingly deeper trenches, aspect ratios, i.e. width-to-depth ratios, of up to 1:40 being embodied. Furthermore, the trench capacitors of the memory cells, which fill the substantial part of the memory chip, are being packed evermore densely in order to further reduce the area required by the individual memory cells. DRAM memory chips are usually implemented with the aid of planar technology, the trenches of the trench capacitors preferably being produced with the aid of an anisotropic etching. The demand to make the trenches ever deeper in conjunction at the same time with a reduced distance between the trenches give rise to the risk of a connection between two adjacent trenches being produced on account of a not exactly perpendicular etching operation, which may lead to a short circuit between the adjacent memory cells. To date, such undesirable short circuits between adjacent memory cells have only been able to be ascertained in the context of a fault analysis in the back-end, i.e. after the end of the entire complicated and expensive fabrication process having approximately 500 individual steps.